BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING
نویسندگان
چکیده
منابع مشابه
BEAR FP A Robust Framework for Floorplanning
This paper presents a hierarchical oorplanning approach for macrocell layouts which is based on the bottom up clustering shape function computation and top down oor plan optimization with integrated global routing and pin assignment This approach provides means for specifying and techniques for satisfying a wide range of constraints physical topological timing and is therefore able to generate ...
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for Interconnect-Driven Floorplanning Zheng Xu , Song Chen , Takeshi Yoshimura 1 and Yong Fang 2 1 Graduate School of Information, Production and Systems, Waseda University, Japan Hibikino2-6-317, Wakamatsu, Kitakyushu, Fukuoka 808-0135, Japan 2 School of Communication and Information Engineering, Shanghai University, China Yanchang Road 149, Shanghai 200072, China E-mail: [email protected]....
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15 صفحه اولA Heuristic Approach for VLSI Floorplanning
Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorplanning is to find a floorplan such that the cost is minimized. This is achieved by minimizing the chip area and interconnection cost. It determines the performance, size, yield and reliability of VLSI chips. We propose a Memetic Algorithm (MA) for non-slicing and hard module VLSI floorplanning pr...
متن کاملOrthogonal Simulated Annealing for Floorplanning
Floorplanning is an essential step in physical design of VLSI. The floorplan design problem is how to place a set of circuit modules on a chip such that the resulting area is minimized. The best known solutions are obtained using simulated annealing based on sequence pairs representing the planning of modules. The conventional simulated annealing algorithm conducts a random perturbation operati...
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ژورنال
عنوان ژورنال: International Journal of High Speed Electronics and Systems
سال: 1992
ISSN: 0129-1564,1793-6438
DOI: 10.1142/s0129156492000060